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| WED3EG6418S-D4 FINAL 128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL FEATURES Double-data-rate architecture Speed of 100MHz, 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect JEDEC standard 200 pin SO-DIMM package Power Supply: 2.5V 0.25V Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. DESCRIPTION The WED3DG6418S is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC NC NC NC NC VSS VSS DQS8 DM8 NC NC VCC VCC NC NC NC NC VSS VSS NC VSS NC VCC VCC VCC NC CKE0 NC NC NC A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10/AP BA1 BA0 RAS# WE# CAS# CSO NC NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC NC VSS NC VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID NC PIN NAMES A0 - A11 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock input Clock input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL FUNCTIONAL BLOCK DIAGRAM WE#,RAS#CAS# CKE0 SO# BA0,BA1,A0-A11 DQ0-7 DM DQ0-7 DQM0 DQ0-7 DM DQ32-39 DQM4 U1 SERIAL PD SCL WP A0 A1 A2 SA0 SA1 SA2 DM DQM1 SDA DQ0-7 DQ8-15 U3 DQ0-7 DM DQ40-479 DQM5 U2 DDR SDRAM U1 DDR SDRAM U2 DDR SDRAM U3 DDR SDRAM U4 DDR SDRAM U4 DDR SDRAM U6 DDR SDRAM U7 DDR SDRAM U8 U4 CK0 120 CK0# DQ0-7 DM DQ16-23 DQM2 DQ0-7 DM DQ48-55 DQM6 PLL U5 U7 DQ0-7 DM DQ24-31 DQM3 DQ0-7 DM DQ56-63 DQM7 U6 U8 White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 8 50 Units V V C W mA DC CHARACTERISTICS (tA = 0 to 70C, VCC = 2.5V 0.2V) Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Min 2.3 2.3 VCCQ/2-50mV VREF-0.04 VREF+0.15 -0.3 VTT+0.76 -- Max 2.7 2.7 VCCQ/2+50mV VREF+0.04 VCCQ+0.3 VREF+0.15 -- VTT-0.76 Unit V V V V V V V V CAPACITANCE (tA = 23C, f = 1MHz, VCC = 3.3V, VREF=1.4V 200mV) Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CK0, CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Min Max 34 34 34 30 30 10 45 10 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL IDD SPECIFICATIONS AND TEST CONDITIONS (Recommended operating conditions, tA = 0 to 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V) Parameter Symbol Conditions One device bank; Active = Precharge; tRC=tRC(MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device banks; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN); tCK=tCK (MIN); lOUT=0mA; Address and control inputs changing once per clock cycle. All device bank idle; Power-down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2; Reads; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); IOUT=0mA Burst=2; Writes; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC(MIN); tCK=tCK(MIN); Address and control input change only during Active Read or Write commands. DDR333@CL=2.5 Max DDR266@CL=2, 2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 840 760 680 mA Operating Current Precharge PowerDown Standby Current Idle Standby Current Active Power-Down Standby Current IDD1 1040 960 880 mA IDD2P 24 24 24 mA IDD2F 200 180 160 mA IDD3P 280 280 225 mA Active Standby Current IDD3N 495 440 360 mA Operating Current IDD4R 1280 1140 960 mA Operating Current IDD4W 1216 1040 815 mA Auto Refresh Current Self Refresh Current IDD5 IDD6 1520 16 1440 16 1315 16 mA mA Operating Current IDD7A 2640 2400 1920 mA * Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT: ONE BANK 1. Typical Case : VCC = 2.5V, T = 25C 2. Worst Case : VCC = 2.7V, T = 10C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 4. Timing patterns -DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR266B (133Mhz, CL = 2.5): tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR333 (166MHz, CL = 2.5) : tCK = 6ns, CL = 2.5, BL = 4, tRCD = 10*tCK, tRAS = 7*tCK Read " A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst. IDD7A : OPERATING CURRENT : FOUR BANK OPERATION 1. Typical Case : Vcc = 2.5V, T = 25C 2. Worst Case : Vcc = 2.7V, T = 10C 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. IOUT = 0mA 4. Timing patterns - DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst -DDR266B (133Mhz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL2 = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR333 (166MHz, CL = 2.5) : tCK = 6ns, CL = 2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com WED3EG6418S-D4 FINAL ORDER INFORMATION Part Number WED3EG6418S335D4 WED3EG6418S262D4 WED3EG6418S265D4 WED3EG6418S202D4 Speed 166MHz/333Mbps 133MHz/266Mbps 133MHz/266Mbps 100MHz/200Mbps CAS Latency CL=2.5 CL=2 CL=2.5 CL=2 PACKAGE DIMENSIONS ALL DIMENSIONS ARE IN INCHES 2.666 MAX. .079 .150 MAX .157+/-.004 .787 PI .091 REF. .165 .071 .449 1.866 .157 MIN. .039.004 White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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